The present disclosure relates to a semiconductor device having a structure in which an insulator layer and a semiconductor layer are laminated on a semiconductor substrate, and to a method of manufacturing the semiconductor device.
For semiconductor integrated circuits including a complementary metal oxide semiconductor (CMOS) transistor, it has been studied to achieve higher integration and a higher operating speed. In recent years, in view of low power consumption, switching from volatile memory to nonvolatile memory has been studied, and, for example, magnetoresistive random access memory (MRAM) has been developed (for example, see Japanese Unexamined Patent Application Publication No. 2010-171166 (JP2010-171166A)).
Usually, a contact electrode connected to a source-drain region of a transistor has been provided on a main-surface side, on which the transistor is formed, of a substrate. However, in recent years, it has been attempted to dispose the contact electrode on a back-surface side of the substrate. For example, JP2010-171166A has discussed as follows. According to this document, while a diffusion layer and a silicide layer of a main element are formed on a surface side of a silicon (Si) substrate, a contact electrode is disposed to extend from a back-surface side of the substrate. This contact electrode from the back-surface side is connected to the silicide layer by passing through the substrate and the diffusion layer. Such a structure increases flexibility in wiring paths and the like, which is advantageous in terms of design.